The present invention relates to a semiconductor device and a designing method thereof, and for example, to a semiconductor device designed by a hierarchical layout designing technique and a designing method thereof.
For example, Japanese Unexamined Patent Application Publication No. 2004-259967 describes a method in which when a physical block is designed by a hierarchical layout designing technique, a wiring inhibition region is set in a boundary side having an external coupling terminal and a shield wire is provided in a boundary side not having an external coupling terminal.